EDN

Analysis of Power Savings from Intelligent Clock Gating

This application note introduces FPGA designers to intelligent clock gating by describing clock gating support in the Xilinx design tools while supplying a detailed analysis of the impact of clock ...
Electronic Design

Sequential Power Optimization Tool Pinpoints Clock-Gating Opportunities At RTL

Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits into existing design flows with industry-standard library, timing, and ...
Semiconductor Engineering

Efficient Gated Clock Design Approach for LFSR

A technical paper titled “A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers” was published by researchers at Università degli Studi di Catania, Italy. “This ...
Semiconductor Engineering

The Vulnerability of Clock Trees to Asymmetric Aging

A new technical paper titled “The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations” was published by researchers at Israel Institute of Technology and The Hebrew University of ...
Electronic Design

Implementing An Efficient RTL Clock Gating Analysis Flow

Lowering the power consumption of consumer products and networking centers is an important design consideration. The same goes for many of the processor cores that go into these devices. This paper ...