Design-Reuse

Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology

Industry's Most Advanced DDR-PHY Solutions Achieved With Denali's Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System SAN JOSE, CA -- May 31, 2007-- Cadence ...
Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
EDN

Synopsys’ New DesignWare DDR Explorer Tool Delivers Up to 20 Percent Improvement in DDR Memory Subsystem Efficiency

DesignWare DDR Explorer enables designers to optimize memory subsystems for power, performance and cost through a graphical simulation and analysis environment Explore and adjust Synopsys' DesignWare ...
EDN

PCI Express x1 PHY supports source synchronous and DDR clocking

Dallas, Tex.— Texas Instruments Inc.'s PCI Express (PCIe) x1 physical layer (PHY) chip has hit the market in volume, providing a low-cost PCI Express endpoint device for a wide variety of sectors such ...
Design-Reuse

True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference

True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries. At the 62 nd Design Automation Conference ...