EDN

Open-source tool links Verilog with TCL

COLORADO SPRINGS, Colo, An open-source tool developed by Acculent Corp., a small design house here, promises to convert tool command language (TCL) scripts into Verilog code, making it easier for ...
EDN

Revised BestBench tool supports Verilog, VHDL

SAN MATEO, Calif. — Testbench tool provider Diagonal Systems AG (Zurich, Switzerland) has introduced BestBench 4.0, a new version of its HDL design and analysis tool that now includes support for ...
Hackaday

Simulating The Learn-by-Fixing CPU

Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
Hackaday

Do We Need A New Hardware Description Language?

When you think about hardware description languages, you probably think of Verilog or VHDL. There are others, of course, but those are the two elephants in the room. Do we need another one?
Electronic Design

Get A 40% Boost In Speed And Utilization Via Enhanced Tools

Development tools for D-Fabrix, Elixent's reconfigurable algorithm processing (RAP) technology, have been upgraded. This means greatly enhanced performance for the D-Sign v1.4 tool suite, including a ...